Ben Marshall
Department of Computer Science, University of Bristol

G. Richard Newell
Microchip Technology Inc., USA

Dan Page
Department of Computer Science, University of Bristol

Markku-Juhani O. Saarinen
PQShield, UK

Claire Wolf
Symbiotic EDA

Keywords: ISE, AES, RISC-V

Abstract

Secure, efficient execution of AES is an essential requirement on most computing platforms. Dedicated Instruction Set Extensions (ISEs) are often included for this purpose. RISC-V is a (relatively) new ISA that lacks such a standardized ISE. We survey the state-of-the-art industrial and academic ISEs for AES, implement and evaluate five different ISEs, one of which is novel. We recommend separate ISEs for 32 and 64-bit base architectures, with measured performance improvements for an AES-128 block encryption of 4x and 10x with a hardware cost of 1.1K and 8.2K gates respectively, when compared to a software-only implementation based on use of T-tables. We also explore how the proposed standard bit-manipulation extension to RISC-V can be harnessed for efficient implementation of AES-GCM. Our work supports the ongoing RISC-V cryptography extension standardisation process.