Transactions on Cryptographic Hardware and Embedded Systems 2026
TETRIS: Automated Design Space Exploration of Randomness-Latency Trade-offs in Masked Hardware
Nilotpola Sarma
Indian Institute of Technology Guwahati, Guwahati, India
Tapish Patidar
Indian Institute of Technology Guwahati, Guwahati, India
Nupur Brahamanya
Indian Institute of Technology Guwahati, Guwahati, India
Chandan Karfa
Indian Institute of Technology Guwahati, Guwahati, India
Keywords: Power Side Channel Security, Masking, Low-latency masking, Low-randomness masking, Design Space Exploration, High-Level Synthesis
Abstract
Given a fixed security order, the randomness and latency of masked hardware present a trade-off. This trade-off has not been structurally examined well enough to enable an efficient search for a user-optimal (randomness/latency-efficient) masked design. Gadget-based masking simplifies masking by replacing each unmasked primitive circuit with a corresponding masked circuit, called a gadget, to realize a larger masked design. These gadgets, in turn, have masking-order-dependent latency-randomness costs, lending a structure to the randomness and latency of gadget-based masked hardware. This structure enables automated Design-Space Exploration (DSE) of gadget-based masked hardware that takes in a user’s constraints on randomness (or latency) to arrive at the latency (or randomness) optimal assignment of gadgets with less area and vice versa. This article introduces a software-level DSE approach, the basis of which is the two DSE algorithms - Minimize Latency under Randomness Constraints (MLRC) and Minimize Randomness under Latency Constraints (MRLC), which are duals of each other. While prior work optimizes masked hardware by formulating a global optimization based on the Boolean Satisfiability Problem (SAT), our results show that gadget-based masked hardware using Probe-Isolating Non-Interference (PINI) gadgets embodies a structured trade-off, enabling efficient heuristic-based solutions rather than relying on heavy global optimizations. This gives our tool comparable or superior area results in under a millisecond - a speedup of up to several orders of magnitude to the State-of-the-Art tools.
Publication
IACR Transactions on Cryptographic Hardware and Embedded Systems, Volume 2026, Issue 4
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Artifact number
tches/2026/a60
Artifact published
November 9, 2026
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BibTeX How to cite
Nilotpola Sarma, Tapish Patidar, Nupur Brahamanya, Chandan Karfa. (2026). TETRIS: Automated Design Space Exploration of Randomness-Latency Trade-offs in Masked Hardware. IACR Transactions on Cryptographic Hardware and Embedded Systems, 2026(4), 597–631. https://doi.org/10.46586/tches.v2026.i4.597-631. Artifact at https://artifacts.iacr.org/tches/2026/a60.