Michal Vojáček
CTU in Prague, Prague, Czech Republic

Martin Novotný
CTU in Prague, Prague, Czech Republic

Keywords: Post-quantum cryptography, FALCON, discrete Gaussian sampling, SamplerZ, rejection sampling, accelerator, low latency, compact, FPGA, pipeline

Abstract

We present the first fully pipelined implementation of FALCON’s Gaussian sampler SamplerZ, which has previously dominated signature-generation time. The design mitigates the latency cost of rejection sampling by launching a new sampling attempt every clock cycle. On the ZCU104 FPGA, our accelerator achieves a Rejection-Inclusive Pair Sampling Time (RIPST) of 100.0 ns, a 5.6x speedup over the best prior area-efficient design. At the same time, it reduces area across all major FPGA resource classes and requires only 30 DSPs, corresponding to a 5.6x/6.7x/17.7x/9.4x (LUT/FF/DSP/BRAM) RIPST-area-product improvement over the strongest prior baseline. Beyond the pipelined architecture itself, we introduce algorithmic and implementation-level optimizations that reduce latency, improve portability, and significantly lower randomness consumption. The resulting design is compact, portable, and reproducible, and provides a practical foundation for future FALCON signing implementations.