International Association for Cryptologic Research

International Association
for Cryptologic Research

Transactions on Cryptographic Hardware and Embedded Systems 2026

Accelerating HQC with Additive FFT


Ming-Shing Chen
IIS and CITI, Academia Sinica, Taipei, Taiwan

Chun-Ming Chiu
IIS and CITI, Academia Sinica, Taipei, Taiwan

Chun-Tao Peng
IIS and CITI, Academia Sinica, Taipei, Taiwan

Bo-Yin Yang
IIS and CITI, Academia Sinica, Taipei, Taiwan


Keywords: HQC, additive FFT, F2 polynomial multiplication, extended CRT


Abstract

This paper presents an accelerated implementation of the Hamming Quasi-Cyclic (HQC) key encapsulation mechanism by leveraging additive Fast Fourier Transform (FFT) for polynomial multiplication (polymuls). A common challenge when applying FFT-based polymuls to HQC are the polynomial degrees fractionally greater than powers of two, making standard FFT polymuls inefficient for those parameters. We introduce a novel combination of additive FFT with the Chinese Remainder Theorem (CRT) to multiply such just-above-power-of-two degree polynomials.Further optimizations are achieved by caching the FFT transforms of the public and secret keys during or after key generation and reusing the transform of the shared random polynomial during the encapsulation and decapsulation processes. This approach significantly reduces redundant computations.The effectiveness of these optimizations is evaluated across various hardware platforms, including x86-64 with AVX2 and Galois Field New Instructions (GFNI), as well as ARM NEON on Apple M1 and Cortex-A72 processors. Benchmarks show that on platforms with long carry-less multiplication instructions like PCLMULQDQ, the proposed caching and reuse strategies allow FFT-based implementations to outpace traditional Toom-Karatsuba methods in the Encap and Decap operations of the HQC scheme, even with comparable raw multiplication speeds. On platforms lacking long carry-less multiplication instructions, the additive FFT approach already gives the superior performance.

Publication

IACR Transactions on Cryptographic Hardware and Embedded Systems, Volume 2026, Issue 2

Paper

Artifact

Artifact number
tches/2026/a28

Artifact published
June 02, 2026

Badge
IACR CHES Artifacts Functional

README

ZIP (13726796 Bytes)  

View on Github

License
CC0 To the extent possible under law, the author(s) have waived all copyright and related or neighboring rights to this artifact.

Note that license information is supplied by the authors and has not been confirmed by the IACR.


BibTeX How to cite

Ming-Shing Chen, Chun-Ming Chiu, Chun-Tao Peng, Bo-Yin Yang. (2026). Accelerating HQC with Additive FFT. IACR Transactions on Cryptographic Hardware and Embedded Systems, 2026(2), 520–544. https://doi.org/10.46586/tches.v2026.i2.520-544. Artifact at https://artifacts.iacr.org/tches/2026/a28.