Ziheng Ma
Beijing National Research Center for lnformation Science and Technology, School of Integrated Circuits, Tsinghua University; State Key Laboratory of Cryptography and Digital Economy Security, Tsinghua University, Beijing, 100084, China

Bohan Yang
Beijing National Research Center for lnformation Science and Technology, School of Integrated Circuits, Tsinghua University; State Key Laboratory of Cryptography and Digital Economy Security, Tsinghua University, Beijing, 100084, China

Wenping Zhu
Beijing National Research Center for lnformation Science and Technology, School of Integrated Circuits, Tsinghua University; State Key Laboratory of Cryptography and Digital Economy Security, Tsinghua University, Beijing, 100084, China

Hanning Wang
Beijing National Research Center for lnformation Science and Technology, School of Integrated Circuits, Tsinghua University; State Key Laboratory of Cryptography and Digital Economy Security, Tsinghua University, Beijing, 100084, China

Yi Ouyang
Beijing National Research Center for lnformation Science and Technology, School of Integrated Circuits, Tsinghua University; State Key Laboratory of Cryptography and Digital Economy Security, Tsinghua University, Beijing, 100084, China

Min Zhu
Wuxi Micro Innovation Integrated Circuit Design Co., Ltd, Jiangsu Wuxi, China

Leibo Liu
Beijing National Research Center for lnformation Science and Technology, School of Integrated Circuits, Tsinghua University; State Key Laboratory of Cryptography and Digital Economy Security, Tsinghua University, Beijing, 100084, China

Keywords: True random number generator, Phase noise, Stochastic model, FPGA

Abstract

A true random number generator (TRNG) is a critical component in ensuring the security of cryptographic systems. Among TRNG implementations, the phase-locked loop-based TRNG (PLL-TRNG) is a widely adopted solution for FPGA platforms due to the availability of a stochastic model. In the previous study, this stochastic model was based on analog noise signals, which potentially led to an oversimplification of the PLL physical process and resulted in an overestimation of entropy. To address this limitation, we extract key platform-specific parameters of the PLL and develop a new stochastic model tailored for multi-output PLL-TRNGs. For the first time, we reveal the effect of the PLL’s bandwidth on the correlation of sampling points and introduce a method for quantitatively controlling sampling point correlations. Finally, we validate the model through on-chip jitter measurements. Experimental results show that the proposed stochastic model accurately describes the behavior of the PLL-TRNG and provides the most conservative entropy lower bound, with a 1.8-fold improvement in jitter resolution.