Transactions on Cryptographic Hardware and Embedded Systems 2025
HIPR:
Hardware IP Protection through Low-Overhead Fine-Grain Redaction
README
HIPR: Hardware IP Protection through Fine-Grain Redaction
This repository contains the artifacts accompanying our paper titled HIPR: Hardware IP Protection through Low-Overhead Fine-Grain Redaction, which has been accepted for publication in TCHES Volume 2025 Issue 3.
The shared artifacts include compressed archives ("*.tgz") for:
- The original and redacted test IPs from the MIT-CEP benchmark suite [1] generated by HIPR.
- The NanGate 15nm standard cell library [2] used for synthesis and simulation.
These artifacts correspond to the evaluation benchmarks reported in our paper: Link
Please cite our work as follows:
BibTeX
@article{Dasgupta_Paria_Bhunia_2025,
title="{HIPR: Hardware IP Protection through Low-Overhead Fine-Grain Redaction}",
volume={2025},
url={https://tches.iacr.org/index.php/TCHES/article/view/12236},
DOI={10.46586/tches.v2025.i3.781-805},
number={3},
journal={IACR Transactions on Cryptographic Hardware and Embedded Systems},
author={Dasgupta, Aritra and Paria, Sudipta and Bhunia, Swarup},
year={2025},
month={Jun.},
pages={781–805}
}
Text
Dasgupta, A., Paria, S., & Bhunia, S. (2025). HIPR: Hardware IP Protection through Low-Overhead Fine-Grain Redaction. IACR Transactions on Cryptographic Hardware and Embedded Systems, 2025(3), 781-805. https://doi.org/10.46586/tches.v2025.i3.781-805
Overview
HIPR is a fine-grain hardware IP redaction technique for ASICs that uses novel transformations to optimize the overhead cost without compromising the security of sensitive IP blocks.
HIPR achieves fine-grain redaction of security-critical Boolean logic cones, sequential logic like FFs, and interconnect randomization as demonstrated below:
Fig. 1: Hardware redaction in HIPR.
The configurable fabric in HIPR utilizes the following components to implement the redacted logic:
- Configurable Look-Up Tables (CLUTs) are used to redact Boolean logic cones.
- Configurable Sequential Blocks (CSBs) are used to realize sequential logic redacted from the designs and dummy sequential elements. Each CSB also contains a CLUT, which can implement existing Boolean logic or introduce dummy logic.
- Configurable Programmable Interconnects (CPIs) are used for interconnect randomization at strategic locations.
Please refer to our paper for more details.
Getting Started
The compressed files ("*.tgz") can be extracted by running the "init.sh" bash script provided:
sh init.sh
Once finished, the evaluation benchmark directory ("./eval_benchmarks_mit_cep") tree should look something like:
./eval_benchmarks_mit_cep/
├── hipr_tX/
│ ├── rdY/
│ │ ├── rdY.hipr_tX.bitstream.txt
│ │ ├── rdY.hipr_tX.rd_io_map.wrapper.v
│ │ ├── rdY.hipr_tX.syn.sdc
│ │ └── rdY.hipr_tX.syn.v
│ │ └── reports_syn/
│ │ ├── rdY.hipr_tX.syn.power.rpt
│ │ └── rdY.hipr_tX.syn.qor.rpt
│ ...
...
├── hipr_tX.tgz
...
├── org/
│ ├── rdY/
│ │ ├── rdY.org.syn.sdc
│ │ ├── rdY.org.syn.v
│ │ └── reports_syn/
│ │ ├── rdY.org.syn.power.rpt
│ │ └── rdY.org.syn.qor.rpt
│ ...
└── org.tgz
Here, $tX: X \in {1,2,3}$ correspond to the HIPR transformations T1/T2/T3 with different combinations of security-aware overhead optimizations, and $rdY: Y \in {1,2,\cdots,10}$ correspond to the 10 test IPs redacted. Please refer to our paper for more details about the transformations and test IPs.
The library directory ("./lib") tree should look like:
./lib/
├── nangate15/
│ ├── sim/
│ │ ├── NanGate_15nm_OCL_conditional.v
│ │ └── NanGate_15nm_OCL_functional.v
│ └── syn/
│ └── NanGate_15nm_OCL_typical_conditional_ccs.db
└── nangate15.tgz
Artifact Details
Original Test IPs
The artifacts shared in the "./eval_benchmarks_mit_cep/org/" directory include the following:
- "rdY/rdY.org.syn.v" : The flattened gate-level netlist for the original test IP Y from the MIT-CEP benchmarks.
- "rdY/rdY.org.syn.sdc" : The design constraints used during synthesis, corresponding to the "rdY.org.syn.v" netlist above.
- "rdY/reports_syn/" : Directory containing the gate-level implementation results for NanGate 15nm corresponding to the "rdY.org.syn.v" netlist, as reported by the synthesis tool (Synopsys Design Compiler).
- "rdY.org.syn.power.rpt" : The power utilization report.
- "rdY.org.syn.qor.rpt" : The synthesis quality of results (QoR).
Redacted Test IPs
The artifacts shared in the "./eval_benchmarks_mit_cep/hipr_tX/" directory include the following:
- "rdY/rdY.hipr_tX.syn.v" : The flattened gate-level netlist for the redacted test IP generated by HIPR from "rdY.org.syn.v" (test IP Y) via transformation TX.
- "rdY/rdY.hipr_tX.syn.sdc" : The design constraints used during synthesis, corresponding to the "rdY.hipr_tX.syn.v" netlist above.
- "rdY/rdY.hipr_tX.bitstream.txt" : The compacted bitstream required to configure the redacted test IP for restoring the true functionality. For a N-bit configuration bitstream, line 1 corresponds to bitstream[0] (LSB) and line N (last line) contains bitstream[N-1].
- "rdY/rdY.hipr_tX.rd_io_map.wrapper.v" : The top-level wrapper over the redacted test IP generated by HIPR to be used for bitstream verification. This wrapper maps the redacted I/O pins (named "rd_io_*") in "rdY.hipr_tX.syn.v" to their corresponding original names, which is required to compare the functional I/O during verification.
- "rdY/reports_syn/rdY.hipr_tX.syn.*.rpt" : The gate-level implementation results (power and QoR) for NanGate 15nm corresponding to the "rdY.org.syn.v" netlist, as reported by the synthesis tool (Synopsys Design Compiler), similar to the original test IPs. The synthesis reports are used to calculate the overhead costs incurred by redaction, compared to the original netlist.
Bitstream Configuration
The redacted IP generated by HIPR contains a daisy-chained shift register to store the configuration bitstream. The bitstream provided in "rdY.hipr_tX.bitstream.txt" can be loaded serially via the "i_bit_si_0" input pin while toggling the configuration clock "config_clk_0" over N clock cycles for a N-bit configuration bitstream, starting from bitstream[0] (line 1) to bitstream[N-1] (line N).
Alternately, the bitstream configuration step can be skipped by directly assigning the configuration bit values from "rdY.hipr_tX.bitstream.txt" to the output pins of the corresponding shift register flops in the"rdY.hipr_tX.syn.v" netlist. As the shift register flops are daisy-chained, they can be easily identified from the netlist using the configuration I/O pins: starting from input "i_bit_si_0" and ending with "o_bit_so_0", where each flop is connected to the clock "config_clk_0".
Standard Cell Library
The gate-level netlists for the original and redacted test IPs are mapped to NanGate 15nm standard cell library for typical/nominal operating conditions (Process: HP, Voltage: 0.8V, Temperature: 25C). The synthesis and simulation library files used by HIPR are shared in the "./lib/nangate15/" directory:
- "syn/NanGate_15nm_OCL_typical_conditional_ccs.db" : The synthesis library in Synopsys DB format.
- "sim/NanGate_15nm_OCL_functional.v" : The functional simulation library for logical verification.
- "sim/NanGate_15nm_OCL_conditional.v" : The conditional simulation library for timing-aware simulations.
The Open-Cell NanGate 15nm library files are available upon request from Silvaco: Link
License
This repository is distributed under the Apache-2.0 license. See LICENCE for more information.
Contacts
If you have any queries, please feel free to contact us:
- Aritra Dasgupta @ aritradasgupta@ufl.edu or aritra.dasgupta.1995@gmail.com
- Sudipta Paria @ sudiptaparia@ufl.edu
- Swarup Bhunia @ swarup@ece.ufl.edu