This directory contains the source files corresponding to the VITI on-chip sensor detailed in “VITI: A Tiny Self-Calibrating Sensor for Power-Variation Measurement in FPGAs”.

Content:

 ./
  |-Spartan6/               : VITI implementation on Xilinx Spartan6 architecture.
    |-iodelay_fsm.v         : Verilog file containing the FSM that controls the delay index of the adjustable input delay element.
    |-tdl.v                 : Verilog file containing the tapped delay line implementation on LUTs.
    |-viti.v                : Verilog file containing the top level module of VITI that includes the FSMs and a block memory element.
  |-UltraSCALE/             : VITI implementation on Xilinx UltraSCALE architecture.
    |-iodelay_fsm.v         : Verilog file containing the FSM that controls the delay index of the adjustable input delay element.
    |-tdl.v                 : Verilog file containing the tapped delay line implementation on LUTs.
    |-viti.v                : Verilog file containing the top level module of VITI that includes the FSMs and a block memory element.
  |-Virtex6/                : VITI implementation on Xilinx Virtex6 architecture.
    |-iodelay_fsm.v         : Verilog file containing the FSM that controls the delay index of the adjustable input delay element.
    |-tdl.v                 : Verilog file containing the tapped delay line implementation on LUTs.
    |-viti.v                : Verilog file containing the top level module of VITI that includes the FSMs and a block memory element.
  |-LICENSE.txt             : Text file containing the license information.
  |-README.txt              : This file (text) containing the information on using VITI.
  |-Sample_exp_setup.zip    : A sample experiment setup on SAKURA-G. Content detailed in the README.txt within the zip archive.

---

To use VITI in a hardware design, add the corresponding iodelay_fsm.v, tdl.v and viti.v files into the project. viti module (viti.v) is the top level module of VITI. Details of the ports are as follows:

------------------------------------------------------------------------------------
| Signal        | Direction| Function                                              |
|---------------|----------|-------------------------------------------------------|
| resetn        | Input    | Active low reset                                      |
| clk           | Input    | Clock                                                 |
| lbus_clk96    | Input    | Input signal to IDELAY_G (can be clk)                 |
| sampling_trig | Input    | Trigger to start sampling                             |
| uart_tx_Done  | Input    | Signal that the transmission of the byte is completed |
| uart_tx_DV    | Output   | Signal that the byte is valid to be transmitted       |
| uart_tx_Byte  | Output   | byte to be transmitted                                |
| busy          | Output   | Signal that VITI is busy/active                       |
------------------------------------------------------------------------------------