This directory contains the source files corresponding to PPWM on-chip sensor detailed in “A Power to Pulse Width Modulation Sensor for Remote Power Analysis Attacks”.

Content:

 ./
  |-Spartan6/               : PPWM implementation on Xilinx Spartan6 architecture.
    |-gate_net.v            : Verilog file containing the gate netowrk implementation on LUTs. Please refer Figure 5 of the paper.
    |-idelay_fsm.v          : Verilog file containing the FSM that controls the delay index of the adjustable input delay element.
    |-ppwm.v                : Verilog file containing the top level module of PPWM that includes the FSM and a block memory element.
  |-UltraSCALE/             : PPWM implementation on Xilinx UltraSCALE architecture.
    |-gate_net.v            : Verilog file containing the gate netowrk implementation on LUTs. Please refer Figure 5 of the paper.
    |-idelay_fsm.v          : Verilog file containing the FSM that controls the delay index of the adjustable input delay element.
    |-ppwm.v                : Verilog file containing the top level module of PPWM that includes the FSM and a block memory element.
  |-LICENSE.txt             : Text file containing the license information.
  |-README.txt              : This file (text) containing the information on using PPWM.
  |-Sample_exp_setup.zip    : A sample experiment setup on SAKURA-G. Content detailed in the README.txt within the zip archive.

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To use PPWM in a hardware design, add the corresponding gate_net.v, idelay_fsm.v and ppwm.v files into the project.
ppwm module (ppwm.v) is the top level module of PPWM.
Details of the ports are as follows:

------------------------------------------------------------------------------------
| Signal        | Direction| Function                                              |
|---------------|----------|-------------------------------------------------------|
| resetn        | Input    | Active low reset                                      |
| clk           | Input    | Clock                                                 |
| lbus_clk96    | Input    | Input signal to IDELAY (can be clk)                   |
| sampling_trig | Input    | Trigger to start sampling                             |
| uart_tx_Done  | Input    | Signal that the transmission of the byte is completed |
| uart_tx_DV    | Output   | Signal that the byte is valid to be transmitted       |
| uart_tx_Bit   | Output   | bit to be transmitted                                 |
| busy          | Output   | Signal that PPWM is busy/active                       |
------------------------------------------------------------------------------------