Transactions on Cryptographic Hardware and Embedded Systems, Volume 2022
A Security Model for Randomization-based Protected Caches
Jordi Ribes-González
Universitat Rovira i Virgili
Oriol Farràs
Universitat Rovira i Virgili
Carles Hernández
Universitat Politècnica de València
Vatistas Kostalabros
Barcelona Supercomputing Center
Miquel Moretó
Barcelona Supercomputing Center
Keywords: Cache side-channel attacks, Timing attacks, Randomization-based protected caches, Randomly-mapped caches, Pseudo-random functions, Security definition
Abstract
Cache side-channel attacks allow adversaries to learn sensitive information about co-running processes by using only access latency measures and cache contention.
This vulnerability has been shown to lead to several microarchitectural attacks. As a promising solution, recent work proposes Randomization-based Protected Caches (RPCs). RPCs randomize cache addresses, changing keys periodically so as to avoid long-term leakage. Unfortunately, recent attacks have called the security of state-of-the-art RPCs into question. In this work, we tackle the problem of formally defining and analyzing the security properties of RPCs. We first give security definitions against access-based cache sidechannel attacks that capture security against known attacks such as Prime+Probe and Evict+Probe. Then, using these definitions, we obtain results that allow to guarantee security by adequately choosing the rekeying period, the key generation algorithm and the cache randomizer, thus providing security proofs for RPCs under certain assumptions.
Publication
Transactions of Cryptographic Hardware and Embedded Systems, Volume 2022, Issue 3
PaperArtifact
Artifact number
tches/2022/a13
Artifact published
August 4, 2022
License
This work is licensed under the Creative Commons Attribution 4.0 International License.
BibTeX How to cite
Ribes-González, J., Farràs, O., Hernández, C., Kostalabros, V., & Moretó, M. (2022). A Security Model for Randomization-based Protected Caches. IACR Transactions on Cryptographic Hardware and Embedded Systems, 2022(3), 1–25. https://doi.org/10.46586/tches.v2022.i3.1-25. Artifact available at https://artifacts.iacr.org/tches/2022/a13