21#include "boost/random/variate_generator.hpp"
22#include "boost/random/mersenne_twister.hpp"
23#include "boost/random/uniform_int.hpp"
62 Emulator(
Architecture arch, boost::variate_generator<boost::mt19937&, boost::uniform_int<uint64_t>> ThreadPrng, uint32_t NrOfPipelineStages);
187 u32 m_memory_shadow_register;
188 u32 m_load_memory_shadow_register;
189 u32 m_store_memory_shadow_register;
193 boost::variate_generator<boost::mt19937&, boost::uniform_int<uint64_t>> m_prolead_prng;
195 u8* validate_address(
u32 address);
196 void clock_cpu(uint32_t randomness_start_addr,uint32_t randomness_end_addr);
200 void clock_cpu_PROLEAD();
202 u32 read_memory_internal(
u32 address,
u8 bytes);
203 void write_memory_internal(
u32 address,
u32 value,
u8 bytes);
206 void write_register_internal(
Register reg,
u32 value);
210 bool execute_PROLEAD(
const Instruction& instr,
::Software::ThreadSimulationStruct& ,
::Software::ProbeTrackingStruct& ,
::Software::HelperStruct&,
bool,
bool&,
const int,
const uint64_t,
const uint32_t,
const uint32_t, std::vector<std::vector<std::vector<uint8_t>>>&);
211 void check_shadow_register_constraints(uint32_t& next_shadow_register_value,
Software::ThreadSimulationStruct& ThreadSimulation, uint32_t address, uint8_t
byte);
213 bool execute(
const Instruction& instr, uint32_t randomness_start_addr, uint32_t randomness_end_addr);
219 void branch_write_PC(
u32 address);
220 void bx_write_PC(
u32 address);
221 void blx_write_PC(
u32 address);
223 void set_exclusive_monitors(
u32 address,
u32 align);
224 bool exclusive_monitors_pass(
u32 address,
u32 align)
const;
226 bool in_priviledged_mode()
const;
227 i32 get_execution_priority()
const;
void write_memory(u32 dst_address, const u8 *buffer, u32 len)
void emulate_PROLEAD(::Software::ThreadSimulationStruct &, ::Software::ProbeTrackingStruct &, ::Software::HelperStruct &, std::vector< std::vector< std::vector< uint8_t > > > &, const int, const uint64_t, const uint32_t, const uint32_t)
u32 read_register(Register reg) const
uint32_t m_pipeline_stages
u32 get_flash_size() const
Emulator(Architecture arch, boost::variate_generator< boost::mt19937 &, boost::uniform_int< uint64_t > > ThreadPrng, uint32_t NrOfPipelineStages)
Emulator(const Emulator &other)
ReturnCode emulateInstantiation(u64 max_isntructions, ::Software::ThreadSimulationStruct &ThreadSimulation, ::Software::ProbeTrackingStruct &ProbeTracker, ::Software::HelperStruct &Helper, std::vector< std::vector< std::vector< uint8_t > > > &ProbeValues, uint32_t randomness_start_addr, uint32_t randomness_end_addr, uint32_t SimulationIndex)
Architecture get_architecture() const
void write_register(Register reg, u32 value)
void read_memory(u32 address, u8 *buffer, u32 len) const
u32 get_ram_offset() const
CPU_State get_cpu_state() const
void set_cpu_state(const CPU_State &state)
void set_ram_region(u32 offset, u32 size)
ReturnCode emulate(u32 end_address, u64 max_instructions, uint32_t randomness_start_addr, uint32_t randomness_end_addr)
bool last_in_IT_block() const
ReturnCode emulate(u64 max_instructions, uint32_t randomness_start_addr, uint32_t randomness_end_addr)
u32 get_flash_offset() const
u32 get_PRNG_randomness()
std::vector< CPU_State > m_pipeline_cpu_states
Emulator(Architecture arch)
void set_flash_region(u32 offset, u32 size)
u32 get_emulated_time() const
InstructionDecoder get_decoder() const
Defines a struct that track meta information for probes.
Defines a struct that tracks metadata during the simulation.
Defines a struct that tracks necessary information for thread simulation.
struct mulator::CPU_State::@0 psr
bool containing_valid_pipeline_values
u32 registers[REGISTER_COUNT]